1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to an impedance calibration apparatus of a semiconductor integrated circuit.
2. Related Art
One way of enhancing the stability of output data from a semiconductor integrated circuit is to configure the data output driver of the semiconductor integrated circuit to maintain a constant impedance value, for example, 240 Ohm.
The data output driver is designed to have a desired impedance value depending on codes.
Therefore, an impedance calibration circuit is provided to perform a code control operation that substantially equalizes the impedance of a D/A conversion circuit, configured by duplicating the data output driver, to 240 Ohm.
FIG. 1 is a block diagram of an impedance calibration apparatus of a conventional semiconductor integrated circuit. Referring to FIG. 1, an impedance calibration apparatus 1 of a conventional semiconductor integrated circuit includes a plurality of voltage dividers 10 and 20 each of which comprising a plurality of resistors, a plurality of comparators 30 to 50, a plurality of counters 60 and 70, and a plurality of D/A converters 80 and 90.
In the impedance calibration apparatus 1, the plurality of D/A converters 80 and 90 receive commands CM1 and CM2 as inputs which enable the D/A converters 80 and 90.
Thereafter, a first code PCODE<0:N> is counted to change the code value thereof.
Furthermore, the impedance calibration apparatus 1 repeats the operation of changing the first code PCODE<0:N> until the level of a code voltage VP generated by converting the first code PCODE<0:N> is between the levels of a first reference voltage VREF1 and a second reference voltage VREF2, and completes the impedance calibration for the first code PCODE<0:N>.
The calibrated first code PCODE<0:N> is then applied to the D/A converter 90, and impedance calibration for a second code NCODE<0:N> is performed in the above-described manner.
The above-described technology requires a time corresponding to a maximum of 512 clocks which is required to perform the process of sequentially increasing the first code PCODE<0:N> and the second code NCODE<0:N>. Accordingly, the areas of the counters 60 and 70 are increased.
Furthermore, since high voltages VDDQ-VSSQ are applied to the plurality of voltage dividers 10 and 20 for generating the first reference voltage VREF1 and the second reference voltage VREF2, a large number of resistors are required. This also serves as a factor which increases the area.